EDN

Design for testability: separating the myths from reality

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a “test re-use” strategy ...
EDN

Design for testability—a boundary-scan primer

Failures have been present in electronic products since the days of vacuum tubes, and despite enormous development and production improvements, no manufacturing technique can guarantee a 100% ...
Semiconductor Engineering

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)

A technical paper titled “Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation” was published by researchers at University of Florida. “Scan-based ...
Semiconductor Engineering

Shift Left In DFT Design

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...