Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...
Yahoo Finance

MicroCloud Hologram Inc. Proposes Quantum AI Simulator Adopting Hybrid CPU-FPGA Method, Achieving Efficient Image Classification Simulation Through Heterogeneous Computing

SHENZHEN, China, Feb. 26, 2026 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, proposed a quantum AI simulator that adopts a ...
Seeking Alpha

MicroCloud Hologram Inc. Builds the Industry's First Multi-FPGA Quantum Fourier Transform Simulation Solution

SHENZHEN, China, Jan. 8, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, launched a brand-new scalable quantum Fourier transform ...
Semiconductor Engineering

Hybrid Emulation

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for Cadence; Russ ...
EDN

SunaptiCAD VeriLogger Extreme: Verilog 2001 simulator provides faster RTL and gate-level simulations

Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing ...
Stockhouse

MicroCloud Hologram Inc. Develops Serial-Parallel Architecture-Based FPGA Quantum Computing Simulation Framework

SHENZHEN, China, Dec. 22, 2025 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, launched a brand-new ...
EDN

Mentor Graphics Introduces FPGA Advantage 5.0

WILSONVILLE, OR — Mentor Graphics Corp. [www.mentor.com] has introduced FPGA Advantage 5.0, an enhanced version of the popular HDL flow that provides designers with an integrated solution and more ...
Design-Reuse

Advantages of FPGA design methodologies

Once used only for glue logic, FPGAs have progressed to a point where system-on-chip (SoC) designs can be built on a single device. The number of gates and features has increased dramatically to ...
Design-Reuse

Market-Driven Open-Cores SoC-Experience

The SoC content is defined by market needs and changes every half a year. The SoC methodology is driven by silicon technology and changes every 16 months. This quick pace of change demands that the ...
Semiconductor Engineering

Why Your FPGA Synthesis Flow Requires Verification

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL ...