Design-Reuse

Microsemi Announces Libero SoC v11.8 Software Providing FPGA Designers Mixed Language Simulation and Best-in-Class Debugging Capabilities

ALISO VIEJO, Calif., Apr. 11, 2017 – Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced ...
Design-Reuse

Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards

ALISO VIEJO, Calif. -- April 19, 2018-- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today ...
Electronics Weekly

Microsemi and MathWorks support FPGA-in-the-loop verification

Microsemi and MathWorks launched hardware support for FPGA-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The integrated FIL workflow with HDL Coder and HDL Verifier ...
New Electronics

HES-DVM simulation acceleration flow for Microchip FPGA designs

Aldec, an expert in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM simulation acceleration flow for Microchip’s PolarFire, ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
NBC News

Microsemi and ESCRYPT Partner to Deliver Cryptographic FPGA Solutions With Enhanced Security

IRVINE, Calif., March 2, 2011 (GLOBE NEWSWIRE) -- Microsemi Corporation (Nasdaq:MSCC), a leading provider of semiconductor technology aimed at building a smart, secure, connected world, and ESCRYPT ...
Electronic Design

Microsemi steps up FPGA cybersecurity with PUF technology

Microsemi has announced the latest addition to its portfolio of cybersecurity capabilities for its flagship FPGAs—SmartFusion2 SoC FPGA and IGLOO2 FPGA—with Physically Unclonable Function (PUF) ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...