Electronic Design

Simplify SoC Development With Embedded Testing

While the use of complex system-on-a-chip (SoC) designs has increased, unfortunately, that hasn't increased the time-to-market window for designers and chip manufacturers. As SoC designs become more ...
EDN

Optimizing the SOC test-development effort

Every business, product, or process can benefit from an ROI (return-on-investment) analysis that enables management to determine how much to invest, how many resources to allocate and, ultimately, ...
Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...
EDN

SoC test requirements debated

BALTIMORE — The prevalence and escalating cost of system-on-chip (SoC) designs are forcing a reexamination of existing approaches to design and test, according to EDA and test industry executives at a ...
Digi Times

Lead times for high-end SoC testers extend to over 6 months, says Advantest

It will take at least six months for Advantest to deliver its high-end SoC testing equipment as shortage of key chip components needed to power the equipment has constrained the company's production, ...
Semiconductor Engineering

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...